ARM: rmobile: Fix module clock controls refer status on Gen3

When referring to the MSTPSR register, it contains the clock
status of SYS, RT, SECURE, and controlling SMSTPCR using this
value has the problem of being affected by the RT and SECURE
status.This patch changes the reference register to SMSTPCR.

Signed-off-by: Hiroyuki Yokoyama <[email protected]>

diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index 060343dfe4df972b35358af3c171ce08a45b566c..8f3d3915f77c40f70fa965e693bb4c214d841bd2 100644 (file)
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
 {
 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
        /* DVFS for reset */
-       mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+       mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
 #endif
        return 0;
 }
@@ -60,7 +60,7 @@ int board_init(void)
        setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
 
        /* Configure the HSUSB block */
-       mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+       mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
        /* Choice USB0SEL */
        clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
                        HSUSB_REG_UGCTRL2_USB0SEL_EHCI);

diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index a1a15316639e7b2280b54835deb117b4aa59ceac..8b15267d7b2d476bf009cb96567963a3fe8db19b 100644 (file)
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
 {
 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
        /* DVFS for reset */
-       mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+       mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
 #endif
        return 0;
 }
@@ -60,7 +60,7 @@ int board_init(void)
        setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
 
        /* Configure the HSUSB block */
-       mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+       mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
        /* Choice USB0SEL */
        clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
                        HSUSB_REG_UGCTRL2_USB0SEL_EHCI);

diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index e549a2efac93c388c28702758fa56ea1220abc65..63550af1f0dd2cd882798520375ba0d8d9d2f959 100644 (file)
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -39,7 +39,7 @@ int board_early_init_f(void)
 {
 #if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
        /* DVFS for reset */
-       mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+       mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926);
 #endif
        return 0;
 }
@@ -60,7 +60,7 @@ int board_init(void)
        setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
 
        /* Configure the HSUSB block */
-       mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+       mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
        /* Choice USB0SEL */
        clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
                        HSUSB_REG_UGCTRL2_USB0SEL_EHCI);